Introduction
Before you can design your own processors we will go through some designs together and gradually build up the foundation and finally you will design your own processors. At the beginning we will design a very simple 8-bit processor.
To design our first 8-bit processor we will follow a top-down approach. As we have seen on the previous page, there is a typical design flow. We will now go through this design flow level by level, starting from a given specification, namely the ISA, and come up with a microarchitecture. From the microarchitecture we derive an RTL description using Verilog. This description is then synthesized with an RTL synthesis tool to a so-called netlist. In the rest of this page, we will now explain the individual steps of the design flow in detail.
Instruction Set Architecture
The entire design process begins with the ISA. The specification of an ISA contains a precise architectural description such as the number of addressable registers, the data word size and, most importantly, all available instructions.
On the right side is an excerpt of an ISA that we will use as a reference for our own 8-bit CPU later on. The instructions are formally defined and described exactly what the instructions should do, which operators are needed and how the instruction must be encoded. Again, the ISA only specifies what needs to be done and not how.
Microarchitecture
Now that we have described what needs to be implemented, it is time to describe how. The microarchitecture is a further step in our design flow and describes the implementation of a given ISA. It is not yet a concrete implementation but rather a formal specification with various design goals in mind. The microarchitecture can be a simple diagram showing all the required blocks and their inputs, outputs and bus sizes.
On the right you can see the microarchitecture for our 8-bit processor. It gives us a rough structure of our processor to be developed, which we can use for orientation. This can be continued in theory by adding more detailed descriptions for the individual blocks. This also depends strongly on the degree of complexity of the processor to be implemented.
Register-Transfer-Level
In the following step of the register transfer level description, a concrete description is formulated using a hardware description language such as Verilog. The sequential and combinatorial circuits are described and therefore how the processor has to behave. In this step, all previously missing information is added.
Among other things, the inputs, outputs and bus widths of the signals are specified. The logic of the individual blocks that we have defined in the microarchitecture is described. This includes, for example, operations such as addition, subtraction and the temporary storage of data in memories. On the right side you can see the source code of a half adder. This module allows us to add two bits together.
Synthesis
Finally, our RTL description is transformed into a so-called gate-level netlist using a synthesis tool. This involves taking the RTL description (which formulated the previous circuits using registers, multiplexers, counters, etc.) and mapping it to logic gates. These logic gates are later mapped to transistors during the physical implementation.
On the right side we find the circuit of the half-adder which was derived by the synthesistool from the RTL description.
