Frequently Asked Questions
To successfully generate an SVG file, all non-synthesizable elements (including test benches) must be removed. It's also beneficial to eliminate
initializations
() of memories and registers. Depending on the complexity (bitwidth or memory elements) of your design, it may be helpful to wrap it in a top module. If only one module is available, it will be flattened; otherwise, a hierarchy will be created. Complex single modules are more likely to be generated when they are part of an hierarchical design and not flattened.
We will filter out files ending with
We will filter out files ending with
_tb.v or _testbench.v and exclude all *.vh files to facilitate successful schematic generation. Testbenches with different naming conventions must also be removed before a schematic can be generated.
No, you cannot. While you can have tabs with both Verilog and SystemVerilog code, during compilation, only the files corresponding to the language selected by the switch button in the toolbar will be used.
To generate a schematic, your design must include both input and output ports and drive these ports. For example, if your design doesn't produce an output signal, the tools will remove the internal logic and retain only the ports.
