The Gorille Instruction Set Architecture

For our 8-bit processor we will define our own ISA. The name of our processor and ISA is Gorille (the French name for Gorilla). The architecture will be a so-called load-store architecture, which means that data must first be loaded into registers before it can be manipulated and cannot be manupulated directly in memory. This also brings us to another important keyword, namely "Reduced instruction set computer" (RISC). This approach describes a design philosophy in which instructions that are easy to realize are part of the ISA. Complicated instructions (for example, a load operation, manipulation of this data and writing it back expressed by an instruction) are avoided. By the way, this approach is called "Complex instruction set computer" (CISC). Our ISA follows a RISC design philosophy.

An instruction normally consists of an opcode (what is to be done) and operands (where the data comes from, which data is to be operated on and where it is to be stored) and immediate values. Below we see the format of an arithmetic instruction. What is noticeable is that our instruction encodes a total of 16 bits instead of 8, even though we are designing an 8-bit processor. The idea is that 8-bit leaves little room for possible instructions and addressing of registers. It is of course possible to define 8-bit wide instructions, but they are more unfriendly to beginners and in our opinion require a little more knowledge of computer architecture.

The opcode field contains the operand, two source registers that serve as operands and one register as destination register. Since the opcode field is 4 bits wide, we can theoretically encode 16 instructions, but we only define 15 instructions and store one byte. There are 3 bits for the register fields, so there will be a total of 8 addressable registers A-F and a register called Program Counter, which stores the memory address for the instruction to be loaded from memory.

The Proposed Instruction Set

In total we will define 15 instructions of which 8 are arithmetic, 4 are jump and 3 are load/store instructions. Below you can see an overview of all defined instructions and their encodings. Fields containing X are so called "I do not care entries" and mean that these single bits can be 0 or 1.

We now have all the information we need to design our processor. In the next step we will define one (of many!) possible microarchitectures.