Bitspinner - HALF-ADDER

HALF-ADDER

Design a 1-bit half adder circuit that efficiently computes the sum and carry-out for two single-bit binary numbers.

half-adder.v
half-adder_tb.v

`default_nettype none 
`timescale 1ns/1ns

`define assert(signal, value) \ 
     if (signal !== value) begin \ 
         $display("ASSERTION FAILED at %2d in %m: signal != value", $time); \ 
         $finish; \ 
     end

module half_adder_tb; 
   
	reg a; 
	reg b;

wire s;
  	wire c;
   
   half_adder dut ( 
     .a(a), 
     .b(b), 
     .s(s), 
     .c(c)
   );

initial begin 
     // Initialize signals 
     a = 0; b = 0;     
     #1;
     $display("Clock toggled at time %1t, a = %0b, b = %0b, s = %0b, c = %0b", $time, a, b, s, c); 
     `assert(s, 1'b0); 
     `assert(c, 1'b0);
     a = 1; b = 0;         
     #1;
     $display("Clock toggled at time %1t, a = %0b, b = %0b, s = %0b, c = %0b", $time, a, b, s, c); 
     `assert(s, 1'b1); 
     `assert(c, 1'b0);
     a = 0; b = 1;    
     #1;
     $display("Clock toggled at time %1t, a = %0b, b = %0b, s = %0b, c = %0b", $time, a, b, s, c); 
     `assert(s, 1'b1); 
     `assert(c, 1'b0);
     a = 1; b = 1;    
     #1;
     $display("Clock toggled at time %1t, a = %0b, b = %0b, s = %0b, c = %0b", $time, a, b, s, c); 
     `assert(s, 1'b0); 
     `assert(c, 1'b1);
     $display("Success!");

$finish; 
     
   end 
   
   initial begin 
     $dumpfile("half_adder.vcd"); 
     $dumpvars;  
   end 
 endmodule

Output:

HALF-ADDER

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