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Final

We have reached the last step and just need to connect our blocks together. We now have a fully functional processor that is capable of running programs we have written ourselves.

In the source code you can see the assign statements that realize the multiplexers we saw on the microarchitecture. The module has two input signals (clk, rst) which, if we wanted to realize the chip, would come from outside the processor. Usually a clock generator is placed on a board which serves as input for the processor, the reset signal could be e.g. a button on a board with which we can reset the processor.

module top_file(
	input wire clk,
	input wire rst
	//output wire [7:0] debug
);

wire [2:0] rs1;
wire [2:0] rs2;
wire [2:0] rd;
wire [2:0] alu_op;
wire we_mem;
wire we_reg;
wire ld_mem;
wire en_jmp;
wire en_immediate;
wire [7:0] immediate;

/*
====================Controler====================
*/

controler controler (
	.i_opcode(opcode),
	.i_flag_zero(flag_zero),
	.i_flag_carry(flag_carry),
	.o_alu_op(alu_op),
	.o_en_jmp(en_jmp),
	.o_ld_mem(ld_mem),
	.o_we_mem(we_mem),
	.o_we_reg(we_reg),
	.o_en_immediate(en_immediate)
);

/*
====================DECODER====================
*/

decoder decoder (
	.i_instruction(instruction),
	.o_opcode(opcode),
	.o_rs1(rs1),
	.o_rs2(rs2),
	.o_rd(rd),
	.o_immediate(immediate)
);

wire [7:0] a;
wire [7:0] b;
wire [7:0] val_for_reg;
wire [3:0] opcode;

//Is mapped to a multiplexer
assign val_for_reg = (ld_mem == 1'b1) ? mem_out : c;

/*
====================REGISTER FILE====================
*/

register_file register_file (
	.i_clk(clk),
	.i_we(we_reg),
	.i_rs1(rs1),
	.i_rs2(rs2),
	.i_rd(rd),
	.i_data(val_for_reg),
	.o_rs1(a),
	.o_rs2(b)
);

wire [7:0] mem_out;
//TODO remove mem_in
wire [7:0] mem_in;

/*
====================DATA MEMORY====================
*/

ram data_mem (
	.i_clk(clk),
	.i_data(b),
	.i_we(we_mem),
	.i_addr(c),
	.o_data(mem_out)
);

//Instruction Memory
wire [7:0] i_pc;
wire [15:0] instruction;

/*
====================INSTRUCTION MEMORY====================
*/

rom inst_mem (
	.i_clk(clk),
	.i_addr(o_pc),
	.o_instr(instruction)
);

wire[7:0] o_pc;
wire [7:0] mux_pc;

//If we dont jump just increase the current pc by +1 (addr)
//Is mapped to a multiplexer
assign i_pc = (en_jmp == 1'b1) ? c : o_pc + 1;

/*
====================PROGRAM COUNTER====================
*/

program_counter pc (
	.i_clk(clk),
	.i_rst(rst),
	.i_pc(i_pc),
	.o_pc(o_pc)
);

wire flag_carry;
wire flag_zero;
wire [7:0] c;
wire [7:0] a_tmp;

//Is mapped to a multiplexer
assign a_tmp = (en_immediate == 1'b1) ? immediate : a;

/*
====================ALU====================
*/

alu alu (
	.i_clk(clk),
	.i_rst(rst),
	.i_a(a_tmp),
	.i_b(b),
	.i_op(alu_op),
	.o_c(c),
	.flag_zero(flag_zero),
	.flag_carry(flag_carry)
);

//assign debug = c;

endmodule

Critical Path

To get a feeling for the execution of an instruction, we will show the critical paths (in red) of three instructions (jmp, add, ld). By critical path in this context, we mean the paths that are crucial for the instructions and emphasize the data flow.

As we can see in the diagrams below, the critical path is different according to the instruction. In the case of the jmp instruction, for example, the new address for the PC register is loaded as an immediate value via the ALU. In the case of the add instruction, the result of the ALU is loaded into the register file and into the addressed target register. In the case of the ld instruction, the output of the ALU is used as the address for a memory access. The corresponding byte is then loaded into the target register. The data flow is directed by the controller.

Final

Critical Path

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Final

Critical Path

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