Bitspinner - FULL-ADDER

FULL-ADDER

Design a 1-bit full adder circuit that efficiently computes the sum and carry-out for two single-bit binary numbers, including an additional carry-in input.

full-adder.v
full-adder_tb.v

`default_nettype none 
 `timescale 1ns/1ns

`define assert(signal, value) \ 
     if (signal !== value) begin \ 
         $display("ASSERTION FAILED at %2d in %m: signal != value", $time); \ 
         $finish; \ 
     end

module full_adder_tb; 
   
	reg a; 
	reg b; 
	reg c_in; 
   
	wire s;
  	wire c_out;
   
   full_adder dut ( 
     .a(a), 
     .b(b), 
     .c_in(c_in),
     .s(s), 
     .c_out(c_out)
   );

initial begin 
     // Initialize signals 
     a = 0; b = 0; c_in = 0;    
     #1;
     $display("Clock toggled at time %1t, a = %0b, b = %0b, c_in = %0b, s = %0b, c_out = %0b", $time, a, b, c_in, s, c_out); 
     `assert(s, 1'b0); 
     `assert(c_out, 1'b0);
     a = 1; b = 0; c_in = 0;         
     #1;
     $display("Clock toggled at time %1t, a = %0b, b = %0b, c_in = %0b, s = %0b, c_out = %0b", $time, a, b, c_in, s, c_out);
     `assert(s, 1'b1); 
     `assert(c_out, 1'b0);
     a = 0; b = 1; c_in = 0;    
     #1;
     $display("Clock toggled at time %1t, a = %0b, b = %0b, c_in = %0b, s = %0b, c_out = %0b", $time, a, b, c_in, s, c_out);
     `assert(s, 1'b1); 
     `assert(c_out, 1'b0);
     a = 1; b = 1; c_in = 0;    
     #1;
     $display("Clock toggled at time %1t, a = %0b, b = %0b, c_in = %0b, s = %0b, c_out = %0b", $time, a, b, c_in, s, c_out);     
     `assert(s, 1'b0); 
     `assert(c_out, 1'b1);
     //FLIP c_in = 0 to c_in = 1;
      a = 0; b = 0; c_in = 1;
      #1;
     $display("Clock toggled at time %1t, a = %0b, b = %0b, c_in = %0b, s = %0b, c_out = %0b", $time, a, b, c_in, s, c_out); 
     `assert(s, 1'b1); 
     `assert(c_out, 1'b0);
     a = 1; b = 0; c_in = 1;         
     #1;
     $display("Clock toggled at time %1t, a = %0b, b = %0b, c_in = %0b, s = %0b, c_out = %0b", $time, a, b, c_in, s, c_out);
     `assert(s, 1'b0); 
     `assert(c_out, 1'b1);
     a = 0; b = 1; c_in = 1;    
     #1;
     $display("Clock toggled at time %1t, a = %0b, b = %0b, c_in = %0b, s = %0b, c_out = %0b", $time, a, b, c_in, s, c_out);
     `assert(s, 1'b0); 
     `assert(c_out, 1'b1);
     a = 1; b = 1; c_in = 1;    
     #1;
     $display("Clock toggled at time %1t, a = %0b, b = %0b, c_in = %0b, s = %0b, c_out = %0b", $time, a, b, c_in, s, c_out);     
     `assert(s, 1'b1); 
     `assert(c_out, 1'b1);
     $display("Success!");

$finish; 
     
   end 
   
   initial begin 
     $dumpfile("full_adder.vcd"); 
     $dumpvars;  
   end 
 endmodule

Output:

FULL-ADDER

Not registered yet? Sign up to Bitspinner

About

Connect

Contact