Bitspinner - ASYNC-D-FLIP-FLOP

ASYNC-D-FLIP-FLOP

Design an asynchronous D-Flip-Flop.

async-d-flip-flop.v
async-d-flip-flop_tb.v

​x
 
module d_flip_flop (
    input wire clk,
    input wire rst,
    input wire d,
    output reg q
);
​
    // TODO
​
endmodule

`default_nettype none 
`timescale 1ns/1ns

`define assert(signal, value) \ 
	if (signal !== value) begin \ 
		$display("ASSERTION FAILED at %2d in %m: signal != value", $time); \ 
		 $finish; \ 
	end

module tb_d_flip_flop;

reg clk;     
reg rst;      
reg d;        
wire q;

d_flip_flop uut (
    .clk(clk),
    .rst(rst),
    .d(d),
    .q(q)
);

// Clock generation
initial begin
    clk = 1; // Initialize clock
    forever #5 clk = ~clk; // Toggle clock every 5 time units
end

// Test sequence
initial begin
  
  rst = 1;
  d = 0;        	
  #10; `assert(q, 0); rst = 0;
  #10; d = 1;
  #10; `assert(q, 1); d = 0; 
  #10; `assert(q, 0); d = 1;
  #10; `assert(q, 1); rst = 1;
  #10; `assert(q, 0); rst = 0;
  #10; `assert(q, 1);
  #1;  `assert(q, 1); rst = 1;
  #1;  `assert(q, 0);
  $finish;

end

// Monitor output
initial begin
  $monitor("Time: %2t | clk %1b | rst: %b | d: %b | q: %b", $time, clk, rst, d, q);
end
  
initial begin 
  $dumpfile("sync_d_flip_flip.vcd"); 
  $dumpvars;  
end

endmodule

xxxxxxxxxx
 
`default_nettype none 
`timescale 1ns/1ns 
​
`define assert(signal, value) \ 
    if (signal !== value) begin \ 
        $display("ASSERTION FAILED at %2d in %m: signal != value", $time); \ 
         $finish; \ 
    end 
​
module tb_d_flip_flop;
​
reg clk;     
reg rst;      
reg d;        
wire q;       
​
d_flip_flop uut (

Output:

xxxxxxxxxx
 
​

ASYNC-D-FLIP-FLOP

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ASYNC-D-FLIP-FLOP

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