Bitspinner - ADDER

ADDER

Design a 4-bit full adder circuit that efficiently performs binary addition and outputs both the sum and carry-out for each bit position.

adder.v
adder_tb.v

`default_nettype none 
 `timescale 1ns/1ns

`define assert(signal, value) \ 
     if (signal !== value) begin \ 
         $display("ASSERTION FAILED at %2d in %m: signal != value", $time); \ 
         $finish; \ 
     end

module adder_tb; 
    localparam integer DATA_WIDTH = 8;

reg [DATA_WIDTH-1:0] a; 
	reg [DATA_WIDTH-1:0] b; 
   
	wire [DATA_WIDTH-1:0] c;    
  	wire carry_out;
   
   adder #(.DATA_WIDTH(DATA_WIDTH)) dut ( 
     .a(a), 
     .b(b), 
     .c(c),
     .carry_out(carry_out)
   );

initial begin 
     // Initialize signals 
     a = 8'h00; b = 8'h00;
     #1;
     $display("Clock toggled at time %1t, a = %8b, b = %8b, c = %8b, carry_out = %0b", $time, a, b, c, carry_out); 
     `assert(c, 8'h00); 
     `assert(carry_out, 1'b0); 
      a = 8'h00; b = 8'h01;
     #1;        
   	 $display("Clock toggled at time %1t, a = %8b, b = %8b, c = %8b, carry_out = %0b", $time, a, b, c, carry_out); 
     `assert(c, 8'h01);
     `assert(carry_out, 1'b0);
      a = 8'h03; b = 8'h03;
     #1;
     $display("Clock toggled at time %1t, a = %8b, b = %8b, c = %8b, carry_out = %0b", $time, a, b, c, carry_out); 
     `assert(c, 8'h06);
     `assert(carry_out, 1'b0);
      a = 8'h0F; b = 8'h0F;
      #1;
   	 $display("Clock toggled at time %1t, a = %8b, b = %8b, c = %8b, carry_out = %0b", $time, a, b, c, carry_out); 
     `assert(c, 8'h1E);
     `assert(carry_out, 1'b0);
      a = 8'hFF; b = 8'h01;
     #1;
      $display("Clock toggled at time %1t, a = %8b, b = %8b, c = %8b, carry_out = %0b", $time, a, b, c, carry_out); 
     `assert(c, 8'h00);
     `assert(carry_out, 1'b1);
      a = 8'hFF; b = 8'h02;
     #1;
      $display("Clock toggled at time %1t, a = %8b, b = %8b, c = %8b, carry_out = %0b", $time, a, b, c, carry_out); 
     `assert(c, 8'h01);
     `assert(carry_out, 1'b1);
      a = 8'hFF; b = 8'h03;
      #1;
      $display("Clock toggled at time %1t, a = %8b, b = %8b, c = %8b, carry_out = %0b", $time, a, b, c, carry_out); 
     `assert(c, 8'h02);
     `assert(carry_out, 1'b1);
     $display("Success!");
     $finish;      
   end 
   
   initial begin 
     $dumpfile("adder.vcd"); 
     $dumpvars;  
   end 
 endmodule

Output:

ADDER

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ADDER

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